The present invention relates to a field effect transistor (FET) mounted on a high frequency LSI for use in multimedia equipment or mobile communication equipment. More particularly, it relates to a structure for realizing a low noise figure and a high maximum oscillation frequency.
Recently, the market of multimedia equipment and mobile communication equipment has been remarkably extended in accordance with increasing needs of consumers, highly developed systems resulting from the development of related arts, and newly found application of mobile communication technology. In the latest prospects, the market scale of the mobile communication service and equipment is estimated to extend to 4.5 trillion yen in 2000 and to 11 trillion yen in 2010. In accordance with such an extension of the market, more practical improvement is desired in transistors and LSIs which can deal with signals in a frequency band of the GHz area suitable to use in communication equipment, a mobile radio communication base station, satellite communication and a broadcasting station.
Conventionally, GaAs ICs, silicon bipolar ICs and BiCMOS LSIs are mainly used as devices for high frequency analog signals meeting such use. However, for example, in the field of the mobile communication, in view of realization of a low cost and small power consumption desired by users or realization of a compact system using a one-chip analog/digital LSI, a high frequency LSI which can deal with both an analog signal and a digital signal by using an FET, in particular, a MOSFET will be a prospective choice.
When a MOSFET is used as a device for a high frequency analog signal, the MOSFET has the following advantages as compared with a bipolar transistor (hereinafter referred to as BJT):
(1) High integration:
Since a MOSFET is applicable to more refinement as compared with a BJT, an area occupied by the transistor on a chip is smaller.
(2) Low distortion characteristic:
The current-voltage characteristic is exhibited as an exponential characteristic in a BJT, whereas it is exhibited as a square characteristic in a MOSFET. Accordingly, adjacency harmonics such as 2f1.+-.f2 and 2f2.+-.f1 do not appear in the MOSFET.
(3) High gain and high efficiency:
The optimization of the dimension (the gate width and the gate length) of a MOSFET results in a high gain and high efficiency. Thus, the number of stages in a module can be decreased, and hence, a compact and inexpensive LSI can be realized.
On the other hand, when a MOSFET is used as a device for a high frequency analog signal, the MOSFET is desired to be further improved in its several characteristics.
FIG. 20 is an equivalent circuit diagram for showing the relationship in characteristics among respective portions of a MOSFET. Now, the characteristic improvements demanded of a MOSFET will be described with reference to FIG. 20.
(1) Improvement in a transconductance gm:
In order to use a MOSFET as a device for a high frequency analog signal, it is necessary to increase a transconductance gm in order to attain a high gain.
A drain current Id of a MOSFET is represented by the following formula (1): EQU Id=(W/2L).multidot..mu.n.multidot.Cox.multidot.(Vgs-Vt).sup.2(1)
wherein .mu.n indicates mobility of electrons, Cox indicates a capacitance of a gate oxide film in a unit area, W and L respectively indicate a gate width and a gate length, Vgs indicates a gate-source voltage and Vt indicates a threshold voltage.
Also, a transconductance gm is represented by the following formula (2): EQU gm=dI/dV=(2.mu.n.multidot.Cox.multidot.Id.multidot.W/L).sup.0.5(2)
As is understood from the formula (2), when the current Id is constant, it is necessary to increase W/L, namely, a ratio between the gate width and the gate length, in order to increase a transconductance gm.
(2) Improvement of cut-off frequency f.sub.T :
A cut-off frequency f.sub.T corresponds to a frequency at which the current gain becomes 1, and is one of indexes for showing the high frequency characteristics of a device. In the cut-off frequency, a margin approximately ten times as large as that of an operation frequency is required.
A cut-off frequency f.sub.T of an FET is represented by the following formula (3): EQU f.sub.T =gm/.pi.(Cgs+Cgd) (3)
wherein Cgs indicates a gate-source capacitance and Cgd indicates a gate-drain capacitance.
As is understood from the formula (3), a cut-off frequency f.sub.T is in proportion to a transconductance gm, and is in inverse proportion to a sum of a gate-source capacitance Cgs and a gate-drain capacitance Cgd. Accordingly, a cut-off frequency f.sub.T can be improved simply by decreasing a gate length L, which also leads to a compact and inexpensive system.
(3) Decrease of noise:
When a MOSFET is used as a device for a high frequency analog signal, it is necessary to decrease noise of the FET itself, so that a weak signal cannot be buried in noise.
In an area where a sum (Rg+Rs) of a gate resistance Rg and a source resistance Rs is large, a minimum noise figure NFmin can be approximated by the following formula (4): EQU NFmin=1+2.pi..multidot.f.multidot.K.multidot.Cgs.sqroot.{(Rg+Rs)/gm}(4)
The formula (4) is designated as Fukui's equation, wherein K is a constant.
As is understood from the formula (4), noise is lower in a transistor having a larger transconductance gm and smaller gate resistance Rg and source resistance Rs.
(4) Improvement of maximum oscillation frequency fmax:
A maximum oscillation frequency fmax corresponds to a frequency at which the power gain becomes 1, and is represented by the following formula (5): EQU fmax=f.sub.T/ 2.sqroot.{Rg(1/W).multidot.(Rds+2.pi.f.multidot.Cgd+Cgs(Ri+Rs)}(5)
wherein Ri indicates a channel resistance.
As is understood from the formula (5), a maximum oscillation frequency fmax is higher as a gate resistance Rg and a source resistance Rs are smaller. Furthermore, although not expressed in the formula (5), it is known that a maximum oscillation frequency fmax is higher as a source inductance Ls is smaller.
Therefore, in a MOSFET disposed in a conventional high frequency LSI, a finger-shaped gate electrode structure is adopted for improving these high frequency characteristics.
FIGS. 21(a) through 21(c) are schematic plan views for showing exemplified layouts of a MOSFET having finger-shaped gate electrodes. Specifically, for example, as is shown in FIG. 21(a), on an active area 101 surrounded with an isolation 100, a large number of gate electrodes 102 are disposed in the shape of fingers. The active areas at both sides of each gate electrode 102 function as a source region 103 or a drain region 104. In each of the source region 103 and the drain region 104, a large number of contacts 106 or 107 are formed so as to decrease a source resistance Rs or a drain resistance Rd. A contact portion 102a of each gate electrode 102 extending over the isolation 100 is provided with a gate contact 105. FIG. 21(b) is a plan view of a MOSFET in which the number of fingers is increased so as to further decrease the gate resistance Rg. FIG. 21(c) is a plan view of a MOSFET in which contact portions 102a are provided at both ends of each gate electrode 102 so as to decrease an equivalent gate resistance Rg.
As is shown in FIG. 22, as a finger length of a gate electrode in one unit cell is increased, the minimum noise figure NFmin is increased. Therefore, in the MOSFET having the layout as shown in FIG. 21(b), while retaining the total gate width constant, the minimum noise figure NFmin is decreased by increasing the number of fingers.
Furthermore, in each of the layouts shown in FIGS. 21(a) through 21(c), a salicide process which can simultaneously decrease a gate resistance Rg, a source resistance Rs and a drain resistance Rd, or a polycide process which can decrease a gate resistance Rg alone is conventionally adopted.
On the other hand, as a device for attaining both a high operation speed and small power consumption demanded of a high frequency semiconductor device, a CMOS device having an SOI (silicon-on-insulator) structure is attracting notice.
FIG. 23 is a sectional view of a conventional SOI-MOSFET including a buried oxide film. As is shown in FIG. 23, a buried oxide film 112 is disposed at a predetermined depth from the top surface of a silicon substrate 111, and an area above the buried oxide film 112 works as an active area (semiconductor area). On the active area, a gate oxide film 117 and a gate electrode 118 are formed, and an impurity at a high concentration is introduced into the active area at both sides of the gate electrode 118, so as to form a source region 113 and a drain region 114. The active area below the gate electrode 118, namely, an area between the source region 113 and the drain region 114, is doped with an impurity having a conductivity type different from that of the impurity included in the source region 113 and the drain region 114 at a concentration on a level for controlling the threshold voltage, and this area works as a channel region 115.
In such an SOI structure, a diffused layer where a current flows in the active area is separated from the silicon substrate 111 by the buried oxide film 112, that is, an insulator. Therefore, as compared with a general bulk MOSFET, a capacitance between the diffused layer and the silicon substrate 111 can be remarkably decreased. Accordingly, a MOS device formed on an SOI substrate can attain both a high speed operation and small power consumption owing to its small parasitic capacitance. As a result, such a MOS device exhibits the following satisfactory characteristics, which cannot be attained by a bulk MOS device.
First, since a substrate bias effect is small, the MOS device can be operated with ease at a low voltage. Second, since the parasitic capacitance is small, the MOS device can be operated at a high speed at a low voltage in accordance with a high frequency signal. Third, since fewer defects are caused by radiation and the like and a soft error hardly occurs, the MOS device has high reliability. Fourthly, the MOS device having a simple structure and high integration can be manufactured through a simple process.
In a MOSFET having a thin film SOI structure including a buried oxide film formed on a semiconductor substrate, two operation modes, that is, a fully depleted (FD) mode in which a Si layer in the channel region is fully depleted in an operation of the transistor and a partially depleted (PD) mode in which a portion not depleted remains in the SOI substrate in the operation, are available. Now, a substrate floating effect, which cannot be negligible for practical use of an SOI device in both modes, will be considered.
In the structure of an SOI transistor, the channel region is floated and a substrate potential cannot be fixed, which is a large difference from a bulk transistor. The most significant problem caused by the substrate floating effect is decrease of a source-drain breakdown voltage. This decrease is brought because holes generated through impact ionization in a high electric field area in the vicinity of the drain region 114 of FIG. 23 are stored below the channel region 115 and increase the potential of the channel region 115, so as to allow a parasitic bipolar transistor to be operated.
In order to suppress this parasitic bipolar transistor effect, various countermeasures have been adopted. The most reliable one among these countermeasures is to fix the substrate potential as in a bulk device (which is a so-called body contact method). FIGS. 24(a) through 24(c) illustrate typical body contact methods. The method shown in FIG. 24(a) is designated as an H-shaped gate method, in which the potential of the channel region is fixed by extending the active area from below the gate electrode 118 at the side of the channel region. The method shown in FIG. 24(b) is designated as a source-tie method, in which a P.sup.+ area is formed in the source region 113, that is, an N.sup.+ area in an NMOS transistor, so that the substrate potential can be prevented from increasing by collecting the generated holes in this P area. The method shown in FIG. 24(c) is designated as a field shield method, in which a field shield electrode is formed in addition to the gate electrode 118, so as to separate adjacent transistors from each other and extract the holes from a separated portion below the field shield electrode.
However, such a MOSFET having the finger-shaped electrodes used as the conventional device for a high frequency analog signal has the following problems:
(1) Decrease of maximum oscillation frequency fmax due to increase of a source inductance:
When the number of the gate fingers is increased as is shown in FIG. 21(b), although the minimum noise figure NFmin is decreased, wires connected with the drain region and the source region are unavoidably formed also in the shape of fingers, and hence, the inductance of these regions is increased owing to the wires. As described above, since a maximum oscillation frequency fmax is in inverse proportion to a source inductance, the increase of the number of fingers leads to the decrease of the maximum oscillation frequency fmax. Accordingly, in a higher frequency region, it is difficult to improve the minimum noise figure NFmin.
(2) In addition, when the number of fingers is increased for realizing low noise, the area occupied by the active area of the semiconductor device is unavoidably increased.
(3) Increased cost resulting from application of a process for decreasing the resistance of the gate electrode and the like:
When the polycide process or the salicide process is adopted in order to decrease the resistance of the gate electrode and the like, the number of procedures is naturally increased, resulting in a high manufacturing cost. Thus, an LSI unit price is increased as compared with a device manufactured through a general process.
(4) Problem in system LSI:
In the case where a high frequency system LSI is to be manufactured by forming plural circuits having a variety of functions on a common substrate, large noise of a part of the circuits largely affects the other circuits, and hence, the aforementioned disadvantages are more noticeably revealed. Accordingly, particularly a circuit desired to have a low noise characteristic is difficult to integrate. As a result, a high frequency system LSI including all circuits mounted on one chip cannot be realized.
(5) Problem in SOI structure:
The conventional body contact methods shown in FIGS. 24(a) through 24(c) have the following problems: A pattern area is increased; the hole extracting effect depends upon a channel width; and a direction of current flow is limited.